Resistive RAMs (ReRAMs) have emerged as leading candidates to displace conventional Flash memories due to their high density, good scalability, low power and high performance. Previous ReRAM designs demonstrating high performance have done so on low density arrays (such as those less than one Gigabit) while those reporting high-density arrays (such as greater than eight Gigabits) were accompanied by relatively low read and write performance.
FIG. 1 illustrates an exemplary embodiment of ReRAM array architecture of a memory device 100. Each chip may comprise several memory blocks. FIG. 1 illustrates memory block 102, comprising memory banks 104. Each memory bank comprises Y-strips 106, or vertical groups of tiles with a common global bitline (CBL). The Y-strip 108 comprises sixteen tiles and one redundant tile, where each tile is a matrix of 8,192 by 256 local bitlines and 2,048 wordlines. The tile 110 comprises 4 subtiles. During a sense operation and a program operation in a bank, 8 tiles (one per Y-strip) are activated simultaneously, each accessing a sub-page for a total sense/program concurrency of 512+16 cells. Since the page size is four times the number of sense/program circuits, there are 4 nibbles, where a nibble is defined as serial accesses to successive bitline addresses during the sense and program sequence performed by the sense and program circuits 112. The complete sense/program unit is a page of 8 sub-pages.
However, during the program operation performed by the sense and program circuits 112, if a page of a sub-tile is activated, the current applied to perform the operation may cause a thermal disturbance to memory cells in neighboring pages, increasing the temperature of the memory cells in the neighboring pages. While program operations can be performed on these neighboring pages, performance (number of verify loops) and reliability (data retention) are significantly degraded by the temperature increase. Consequently, a period of time elapses, generally, before operations are performed on the neighboring pages, thus increasing the program operation time.
Therefore, there is a need in the art for page programming sequences and assignments in memory devices that reduce program operation time in accordance with exemplary embodiments of the present invention.